This invention relates to memory circuitry and, in particular, to improved latching-type sense amplifiers suitable for use with random access memory (RAM) systems.
Latching-type sense amplifiers have been used in dynamic semiconductor memories such as are described in articles entitled "VMOS Technology Applied to Dynamic RAM's" by Kurt Hoffmann and Reinhard Losehand (FIG. 2), and "An 8 mm.sup.2, 5 V 16K Dynamic RAM Using a New Memory Cell" by Gunther Meusburger, Karlheinrich Horninger, and Gerold Lindert (FIG. 2(a)), which appear in the IEEE Journal of Solid-State Circuits, Volume SC-13, No. 5, October 1978, at pages 617-622 and 708-711, respectively. These sense amplifiers consist essentially of first and second cross-coupled transistors and of third and fourth transistors whose drain-source output circuitry couples the cross-coupled pair of transistors to bit lines of the memory. The third and fourth transistors act as buffers between the bit lines, which have relatively heavy capacitance associated therewith, and the cross-coupled pair of transistors. Read/write circuits, which are also denoted as input/output (I/O) circuits, are connected directly to the bit lines or directly to the cross-coupled pair. The third and fourth transistors are either biased so as to make them continuously on during all cycles of the memory or are biased on during only selected portions of the memory cycle. The sense amplifiers described hereinabove tend to provide either slower memory access or cycle time than is desirable and/or incur high current spikes that can cause a loss in memory operating margins.
It would be desirable to have a sense amplifier that facilitates relatively fast semiconductor memory access and cycle times and which reduces the magnitude of current spikes.